During the preparation of a binary machine language program for execution on a microprocessor a number of operations are effected. Such operations include translation of a representation of the program in a source language into the binary machine language, binding symbols to addresses, and debugging the program. The process of translation may be accomplished by a compiler which receives as its inputs a high level language representation of the program, or an assembler which receives as its inputs an assembly language representation of the program.
A problem exists in the preparation of programs for microprocessors which are still in the process of development in that the architecture of the instruction set may alter during development of the microprocessor. Such changes may take the form of altering the size and location of instruction operands or the writing of new instructions.
Assemblers are typically programs which translate instructions comprising mnemonics and operands into binary representations and which translate the mnemonics and operands (including immediate data) into corresponding binary values, viz opcodes and encoded operands. Each instruction comprises a set of contiguous bit fields which fully characterize the instruction, where a bit field is a sequence of contiguous bits.
The assembler must ensure for example that the binary representation of operands are located in the correct bit field and this is typically achieved by hard coding of control information into the assembler program. Likewise, if encoding a particular operand involves a specified operation to encode it, for example, division by 2, this operation is typically hard coded into the assembler.
A problem which arises if the instruction set architecture is changed is that re-writing of the features hard coded into the assembler, amongst other things, will be necessary to account for the changes.
It is an object of the present invention to at least partially overcome the difficulties of the prior art.
It is an object of some embodiments of the invention to provide a system for generating an assembler which system takes into account updates in processor instruction architecture so that the resultant assembler complies with such updates.